1. Field of the Invention
The present invention relates to a digital filter and a filtering method and, more particularly, to a digital filter and a filtering method that decimate the digital signal which is A/D converted at an oversampling frequency.
2. Description of Related Art
Digital audio equipment use an oversampling A/D converter that samples an analog signal at a higher frequency than an output sampling frequency in order to improve the signal-to-noise ratio (S/N) and increase the dynamic range.
As the oversampling A/D converter, a Delta-Sigma (ΔΣ) A/D converter that outputs 1-bit data of a high- or low-level signal at an oversampling rate (frequency) is known. Further, a decimation filter is used to decimate the signal oversampled by the ΔΣ A/D-converter to a given sampling rate.
For example, the ΔΣ A/D converter converts from an analog signal into a 1-bit digital data at 3 MHz sampling rate, and the decimation filter reduces the sampling rate of the digital data to 48 KHz, thereby outputting a 16-bit digital signal. The digital signal with a desired sampling rate is thereby obtained.
Such a decimation filter requires a high-order, complicated digital filter to obtain a desired sampling rate in one decimation step. Therefore, it is common to perform a plurality of decimation steps and use a low-order, simple digital filter.
A decimation filter having a multiplier is described, for example, in Akira Yukawa, “Oversampling A-D conversion technology”, Nikkei Business Publications, Inc., Dec. 25, 1990, p. 119. FIG. 4 shows the configuration example of a multiplier decimation filter. This decimation filter includes a first-stage decimation filter 120 and a second-stage decimation filter 130.
For example, the first-stage decimation filter 120 decimates the output signal from an A/D converter (ADC) at a decimation ratio of 1/2. The second-stage decimation filter 130 decimates the output signal from the first-stage decimation filter 120 at a decimation ratio of 1/16.
The first-stage decimation filter 120 is a moving average filter, for example, which is composed of a decoder 121 as shown in FIG. 4. A 1-bit output signal if input to the decoder 121 from the ADC. The decoder 121 calculates a moving average of a plurality of bits and outputs it to the second-stage decimation filter 130.
The second-stage decimation filter 130 is a finite impulse response (FIR) filter, for example. It is composed of a filter coefficient ROM 131, an address counter 132, a multiplier 133, an adder 134, a three-stage shift register 135, and a selector 136.
The address counter 132 counts up or down and sequentially outputs the counted address. The filter coefficient ROM 131 stores filter coefficients of given words and sequentially outputs the filter coefficient of the address specified by the output from the address counter 132.
The multiplier 133 receives the signal from the decoder 121 and the filter coefficient from the filter coefficient ROM 131. The multiplier 133 multiplies the signal values.
The adder 134 receives a multiplication result from the multiplier 133 and a signal from the three-stage shift register 135. The adder 134 adds the signal values. The three-stage shift register 135 sequentially stores three addition results from the multiplier 133 and outputs the oldest addition result to the adder 134 so that the adder 134 further adds the value. After the adder 134 repeats the addition N times, the selector 136 allows the values stored in the three-stage shift register 135 to be output to the outside.
This example uses a three-stage shift register to store addition results for multiplexing, thereby simplifying the circuit configuration. However, use of a multiplier in a decimation filter complicates the circuit configuration and increases the circuit size.
To overcome the above problems, a decimation filter which does not have a multiplier is proposed in Japanese Unexamined Patent Application Publication No. 4-245712 (Maruyama), for example. FIG. 5 shows the configuration example of a decimation filter without multiplier. The decimation filter includes a first-stage decimation filter 120 and a second-stage decimation filter 140.
The first-stage decimation filter 120 is a moving average filter which is composed of a decoder 121 as in FIG. 4. The second-stage decimation filter 140 is a FIR filter, for example, which is composed of a controller 141, a filter coefficient ROM 142, a shifter 143, a complementer 144, a reset circuit 145, an adder 146, and an accumulator 147.
In this decimation filter, the second-stage decimation filter 140 performs a given operation on a filter coefficient according to the output from the first-stage decimation filter 120. To describe the operation principle of the second-stage decimation filter 140, the first-stage decimation filter 120 is described below.
The first-stage decimation filter 120 is a second-order 2-tap moving average filter. The transfer function of this filter is expressed by:
                              H          ⁡                      (            z            )                          =                                            1              4                        ⁢                          (                              1                +                                  z                                      -                    1                                                              )                        ⁢                          (                              1                +                                  z                                      -                    1                                                              )                                =                                    1              4                        ⁢                          (                                                z                  0                                +                                  2                  ⁢                                      z                                          -                      1                                                                      +                                  z                                      -                    2                                                              )                                                          Formula        ⁢                                  ⁢        4            
The 1-bit output from the ADC is the input to the second-order 2-tap moving average filter and assigned to “Z” of Formula 4. In Formula 4, Z0 indicates the present input, Z−1 indicates the immediately previous input, and Z−2 indicates the second previous input. Thus, the three-bit data from the present to the second previous data is input to the second-order 2-tap moving average filter. The second-order 2-tap moving average filter calculates their moving average and outputs a result.
FIG. 6 shows the frequency characteristics of the second-order 2-tap moving average filter. In FIG. 6, the horizontal axis indicates frequency and the vertical axis indicates gain. The frequency is a value normalized with a sampling frequency (sampling rate). For example, the frequency 0.5 represents 0.5 times the sampling frequency, which is, half the sampling frequency. As shown in FIG. 6, the gain is 0 dB when the frequency is 0, and the gain decreases as the frequency increases. The gain being 0 dB means that an input signal is output without any change, and the gain being −100 dB means that a signal attenuated by 100 dB from the input signal is output. Thus, the second-order 2-tap moving average filter is a low-pass filter which lets through a low frequency component and attenuates a high frequency component. For example, the gain is attenuated to about −35 dB at the frequency 0.45 and it is attenuated to about −100 dB at the frequency 0.5.
If, in the 1-bit data output from the ADC, a high level is represented as “+1” and a low level as “−1”, the output of the first-stage decimation filter 120 is “0”, “±0.5” or “±1” from Formula 4. The second-stage decimation filter 140 multiplies the output of the first-stage decimation filter 120 and a filter coefficient and adds the result, thereby obtaining an output, as is the case with FIG. 4. Thus, it multiplies a limited value of “0”, “±0.5” or “±1” which is the output of the first-stage decimation filter 120, and a filter coefficient. Since the value to be multiplied with the filter coefficient is limited, the multiplication can be implemented by performing the operation shown in Table 4 on the filter coefficient.
TABLE 4outputoperation on filter coefficient+0.5none+11-bit shift−0.5complementation−11-bit shift, complementation0reset
Table 4 shows the output of Formula 4 and the operation on the filter coefficient in the second-stage decimation filter 140. In the example of Table 4, “+0.5” is a reference value. When the output is “+0.5”, the filter coefficient is not changed since “+0.5” is a reference value. When the output is “+1”, the filter coefficient is 1-bit shifted since “+1” is twice the value of “+0.5”. When the output is “−0.5”, the filter coefficient is complemented since “−0.5” is the negative value of “+0.5”. When the output is “−1”, the filter coefficient is 1-bit shifted and complemented since “−1” is the negative value of “+1”. When the output is “0”, the filter coefficient is reset since multiplication of “0” means no operation. The same effect as the multiplication is thereby obtained. Thus, the second-stage decimation filter 140 may be implemented by the combination of “1-bit shift” “complementation”, and “reset”. Table 5 shows a truth table representing the operation of Table 4.
TABLE 5Z0Z−1Z−2ShiftCompZerooutput000110−1001010−0.50100010011000+0.5100010−0.51010010110000+0.5111100+1
Table 5 shows the input and the output of Formula 4 and the operations performed in the second-stage decimation filter 140. In Table 5, “Z0”, “Z−1”, and “Z−2” are the inputs to the Formula 4 and “output” is the output from Formula 4. Since the input to the first-stage decimation filter 120 is 3 bits from Formula 4, the truth table has 8 patterns. In Table 5, “Shift”, “Comp”, and “Zero” indicate the operations performed in the second-stage decimation filter 140, which correspond to the operations on the filter coefficient shown in Table 4. The “Shift” represents 1-bit shift of a filter coefficient, “Comp” represents complementation of a filter coefficient, and “Zero” represents reset of a filter coefficient.
In FIG. 5, if the input signal of Table 5 is input from the ADC to the first-stage decimation filter 120, the first-stage decimation filter 120 outputs the output signal of Table 5 to the controller 141 of the second-stage decimation filter 140. The controller 141 outputs a control signal for making the shifter 143, the complementer 144, and the reset circuit 145 operate according to Table 5. The controller 141 outputs a control signal for controlling the operation of the shifter 143 if “Shift” is 1 in Table 5, a control signal for controlling the operation of the complementer 144 if “Comp” is 1, and a control signal for controlling the operation of the reset circuit 145 if “Zero” is 1. The filter coefficient ROM 142 sequentially outputs a filter coefficient, and the shifter 143, the complementer 144, and the reset circuit 145 perform a given operation on the filter coefficient according to the control signal from the controller 141.
The adder 146 receives the filter coefficient from the filter coefficient ROM 142, the operation result from the shifter 143, the complementer 144, and the reset circuit 145, and a signal from the accumulator 147. The adder 146 adds these signal values. The addition result of the adder 146 is sequentially stored into the accumulator 147. Thus, the adder 146 adds the operation result of the shifter 143, the complementer 144, and the reset circuit 145 to the operation result up to the previous operation, and the accumulator 147 stores the addition result. After repeating this process N times, the accumulator 147 outputs its contents.
This configuration allows implementation of a decimation filter without a multiplexer. The configuration of FIG. 5, however, only allows the operations of “1-bit shift” “complementation”, and “reset” on the filter coefficients, and it is not applicable to the case where the first-stage decimation filter outputs a value different from the values shown in Table 4. It is therefore not applicable to the case where the first-stage decimation filter is a third or higher order 2-tap moving average filter.
As described above, it has now been discovered that a conventional digital filter has a problem that, when decimating an output signal of a third or higher order 2-tap moving average filter or the like, a circuit without a multiplexer as taught by Maruyama cannot be used and a multiplexer is required, complicating the circuit configuration.